The present invention relates to a semiconductor device, and more particularly to an improved layout of transistors near LCD (liquid crystal display) drive terminals in a CMOS semiconductor device.
FIG. 1 illustrates a conventional LCD drive terminal circuit. In this LCD drive terminal circuit, as shown in FIG. 1, three resistors 520 are coupled in series between an electric source 502 and a ground terminal 503 so as to divide a source voltage VDD of the electric source 502 to output a ground potential, the 1/3 VDD potential, the 2/3 VDD potential or the VDD potential from an input-output terminal 501. Diode-connected P-type MOSFET 514 and N-type MOSFET 519 are connected at their drains which are linked to the input-output terminal 501. Between the coupling terminals of the three resistors 520 and the input-output terminal 501, a P-type MOSFET 510 of which its gate is input by an inverted signal using an inverter 530 and receiving functions as a pass transistor, a couple of P-type MOSFET 511 and N-type MOSFET 515 receiving at their gates complementary signals using an inverter 531 and which function as a CMOS pass transistor, a couple of P-type MOSFET 512 and N-type MOSFET 516 receiving at their gates by complementary signals using an inverter 532 and which function as a CMOS pass transistor, and an N-type MOSFET 517 functioning as a pass transistor are connected in parallel.
FIG. 2 shows the relationship between input control signals a, b, c and d supplied to the circuit shown in FIG. 1 and potentials output from the input-output terminal 501.
The control signals a, b, c and d are controlled so that one of these signals may be a high level. When the control signal a is high, the N-type MOSFET 517 is "ON" to output the ground signal from the input-output terminal 501. When the control signal b is high, both the P-type MOSFET 512 and N-type MOSFET 516 are "ON" to output the 1/3 VDD signal from the input-output terminal 501. When the control signal c is high, both the P-type MOSFET 511 and N-type MOSFET 515 are "ON" to output the 2/3 VDD signal from the input-output terminal 501. When the control signal d is high, the P-type MOSFET 510 is "ON" to output the VDD signal from the input-output terminal 501.
Various conventional methods are used for driving the LCD, but in general, in order to display many patterns, electrically, a matrix type driver shown in FIG. 3 is used. Lines COMO to COM3, S0 and S1 are inputs of the LCD and can be driven by the LCD drive terminal circuit shown in FIG. 1.
FIG. 4A and 4B show display patterns of the LCD and are used for displaying numerals. For example, when displaying a numeral "1", patterns 1 and 2 are ON and the rest is OFF. The line S0 is connected to patterns 0 to patterns 3 and the line S1 to patterns 4 to pattern 7, as shown in FIG. 4A. The line COM0 is connected to pattern 0 and pattern 4, the line COM1 to pattern 1 and pattern 5, the line COM2 to pattern 2 and pattern 6, and the line COM3 to pattern 3 and pattern 7, as shown in FIG. 4B.
Voltages shown in FIG. 5 are supplied to the lines COMO to COM3, S0 and S1. Hence, a large voltage amplitude is applied between COM1 and S0 (see COML-S0 in FIG. 5) and between COM2 and S0 (see COM2-S0 in FIG. 5), and patterns 1 and 2 turn ON.
A voltage amplitude is small between COM0 and S0 and between COM3 and S0, as shown by COMO-S0 and COM3-S0 in FIG. 6, and patterns 0 and 3 are OFF. Similarly, a voltage amplitude is small between COM0 to 3 and S1, and patterns 4 to 7 are OFF.
FIG. 7 schematically shows one example of LCD drive terminals of the circuit shown in FIG. 1. The P-type MOSFET 514 and the N-type MOSFET 519 act as protective elements against electrostatic destruction.
FIG. 8 shows the detailed layout and wiring of the LCD drive terminals shown in FIG. 7.
In FIG. 8, a P-type diffusion layer 601 provides the source and the drain of the P-type MOSFET 514, and polysilicon 604 provides the gate of the same. A second aluminum (A1) 607 is a wire for supplying a source potential to the source and the gate of the P-type MOSFET 514.
An N-type diffusion layer 602 provides the source and the drain of the N-type MOSFET 519, and a polysilicon 603 provides the gate of the same. Another second aluminum 606 is a wire for supplying a ground potential to the source of the N-type MOSFET 519.
A first aluminum 609 couples the drains of the P-type MOSFET 514 and the N-type MOSFET 519, the drains of the P-type MOSFETs 510 to 512 and the drains of the N-type MOSFETs 515 to 517 to a pad 541 corresponding to the input-output terminal 501.
As is well-known, in general, destruction due to static electricity is liable to occur in a MOS type IC. For example, as shown in FIG. 9, when high static electricity is applied to an input-output terminal, a current flows in a PN junction connected to this terminal to destroy the PN junction, or dielectric breakdown occurs in a gate formed by a thin oxide film.
In order to reduce such destruction or breakdown due to static electricity, usually, large size protective elements such as the N-type MOSFET 519 and the P-type MOSFET 514, as shown in FIG. 7, are mounted on the input-output terminal of the MOS type IC to diminish a current density caused when the static electricity is applied to the input-output terminal, resulting in preventing destruction or breakdown.
An LSI using both a P-type MOSFET and an N-type MOSFET is called a CMOS LSI which involves a problem usually called "latch-up".
This latch-up is a phenomenon of current flow in a parasitic thyristor annexed to a CMOS structure and may bring about destruction of a chip at the worst.
FIG. 10 shows a parasitic thyristor. A parasitic thyristor of a PNPN structure is formed between an electric source and a ground. When a latch-up is caused in this part, a large current flows between the electric source and the ground shown in FIG. 10.
The latch-up happens most frequently in a CMOS semiconductor device when higher voltage than the source voltage or a lower voltage than the ground voltage, that is, an overvoltage is applied to the input-output terminal.
As shown in FIG. 11, usually, some P-type or N-type diffusion layer is connected to the input-output terminal 501. For example, when a lower voltage than the ground voltage is applied to the input-output terminal 501, the PN junction between the drain of the N-type MOSFET 519 connected to the input-output terminal 501 and a P-type substrate coupled to the ground has a forward bias and a large current flows therein.
A part of the large current flowing in the P-type substrate reaches a parasitic thyristor shown in FIG. 10, which is positioned near the terminal part of the CMOS type IC shown in FIG. 11.
In the parasitic thyristor shown in FIG. 10, the P-type substrate provides the gate of the thyristor, and, when it is sufficient for the reached current to allow the thyristor to be conductive, the parasitic thyristor becomes conductive and turns to latch-up.
Since this latch-up may bring about the destruction of the chip, the chip is designed so that the latch-up phenomenon is prevented as far as possible. Usually, the P-type and N-type diffusion layers connected directly to the input-output terminal, in particular, are separated from other P-type and N-type diffusion layers at a predetermined distance. As described above, when an overvoltage is applied to the input-output terminal, the P-type and N-type diffusion layers connected directly to the input-output terminal can act as escape paths for the current which causes the latch-up and hence can prevent the sufficient current from reaching the parasitic thyristor causing its conductive state and latch-up.
In the circuit shown in FIG. 7, in order to prevent the latch-up, a predetermined distance is given between the N-type MOSFET 519 and the P-type MOSFET 514, and between the P-type MOSFET 514 and the P-type and N-type MOSFETs 510 to 513 and 515 to 517.
In a semiconductor device for implementing the LCD drive function, usually, the LCD includes many display elements and thus the number of drive terminals also increases.
In the foregoing conventional LCD drive terminal circuit, sufficient space is ensured around each of the many LCD drive terminals for preventing the latch-up. As a result, the chip size is enlarged and the production cost increases.